Analog Layout Design Engineer

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Role: Analog Layout Design Engineer

Location: Santa Clara, CA (Onsite)

Employment Type: Contract

Interview: Phone/Skype

 

Job Description:

Looking for an experienced Analog Layout Design Engineer with expertise in CMOS FinFET technologies (7nm, 3nm), high-speed IC layout, and EDA tools.

Analog & RF Layout for High-Speed Applications

Ultra-Low Power ASIC/SOC Design

EDA Tools: Cadence, Mentor, Synopsys

Mixed-Signal Layout (TIAs, CMOS Drivers, Data Converters, PLLs)

Python Scripting & Floor Planning

#AnalogDesign #RFLayout #CMOSFinFET #EDA #Python #Cadence #MentorGraphics #Synopsys

All your information will be kept confidential according to EEO guidelines.