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PCB Design Engineer

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Job Description - PCB Design Engineer

Company Description

At Fusion Plus Solutions Inc, we believe that it’s an exceptional company - a company of people proud of the work they do and the solutions they provide. By understanding what drives our specialty industries, becoming involved in our communities on a professional and personal basis, following a disciplined process of identifying quality candidates, partnering with employers to understand their core business and their employment requirements, and delivering exceptional service, we achieve great results for all concerned. Fusion Plus is providing traditional staffing services, professional and technical staffing and management services to some of the country's leading companies with highest quality of service.

Website

https://fusionplusinc.com/

Job Description

Role: PCB Design Engineer

Location: Santa Clara, CA ( Day 1 Onsite)

Type: Fulltime/Contract to hire and subcon

Job Description: Senior Electrical Engineer - Advanced Semiconductor Packaging and Integration

Position Overview

We are seeking a highly experienced Senior Product Lead with a robust background in Advanced Semiconductor Electronics and ASIC Design. The ideal candidate will possess extensive knowledge in mixed-signal design, chiplet design, and advanced packaging. This role demands a deep understanding of both BEOL and FEOL semiconductor processing, as well as current packaging and substrate technologies for advanced packaging.

Responsibilities

•           Lead the design and development of advanced semiconductor electronics and ASICs, ensuring high performance and reliability.

•           Develop and optimize mixed-signal designs, balancing analogue and digital circuit requirements.

•           Oversee semiconductor processing and advanced packaging technologies to enhance device performance and manufacturability.

•           Integrate High Bandwidth Memory (HBM) and Low Power Double Data Rate (LPDDR) memory into system designs for improved efficiency and speed.

•           Implement chiplet integration techniques, focusing on high-speed chiplet I/O and interconnects.

•           Ensure signal integrity and power integrity throughout the design and development process.

•           Automate chip layout generation and format conversion to streamline design workflows.

•           Design printed circuit boards (PCBs) with a focus on performance, reliability, and manufacturability.

•           Conduct thermal simulations to optimize thermal management and ensure device reliability under various operating conditions.

•           Collaborate with cross-functional teams to ensure seamless integration and timely delivery of projects.

•           Mentor and guide junior engineers, fostering a culture of continuous learning and innovation.

Requirements

•           M.S in Electrical Engineering, Computer Engineering, or a related field.

•           Extensive experience in advanced semiconductor electronics and ASIC design.

•           Proficiency in mixed-signal design and semiconductor processing techniques.

•           Strong knowledge of advanced packaging technologies, including HBM and LPDDR integration.

•           Experience with chiplet integration, high-speed chiplet I/O, and interconnects.

•           Expertise in signal integrity, power integrity, and automated chip layout generation.

•           Proven track record in PCB design and thermal simulations.

•           Published works or patents in semiconductor technologies are highly desirable.

•           Excellent leadership, communication, and project management skills.

•           Ability to work collaboratively in a fast-paced and dynamic environment.

Preferred Qualifications

•           Ph.D. in a relevant field.

•           Experience with leading industry-standard design and simulation tools.

•           Published works or patents in semiconductor technologies.

•           Excellent leadership, communication, and project management skills.

Additional Information

All your information will be kept confidential according to EEO guidelines.

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