Applications Engineer Physical Design/Fill - (Design Enablement)

icon briefcase Job Type : Full Time

Number of Applicants

 : 

000+

Click to reveal the number of candidates who applied for this job.
icon loader
icon loader

This job is no longer accepting applications.

Scroll down below to view similar jobs .

Job Description - Applications Engineer Physical Design/Fill - (Design Enablement)

Applications Engineer Physical Design/Fill - (Design Enablement) page is loaded

Applications Engineer Physical Design/Fill - (Design Enablement)

Apply

locations

US, Oregon, Hillsboro

US, California, Santa Clara

US, Arizona, Phoenix

time type

Full time

posted on

Posted 2 Days Ago

job requisition id

JR0262670

Job Details:

Job Description:

At Intel, Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products in the marketplace. You will directly drive and work with DE cross teams to ensure that design-kits for customer enablement are lead cutting edge technologies. In addition, you will work with our customers to outline and collaborate on requirements with internal partners to define the scope, execution planning, and competitive solutions to meet the customer's needs.
This position's supporting role will drive solutions for ASIC tools/flows when customers use intel PDK collaterals in Physical design domain. You will also lead the collaboration across ourTD/DE/QnR organizations to find the best path to resolve the issue, along with owning/maintaining training documents, user guide, and customer ticket support.
As a DEAS (Design Enablement Application and Support) key member, you will use your communication skills to interact with customers directly while applying analytical problem-solving capability to identify the key requests, root-causing the issue, and teamwork with DE stakeholders to support and enable the customer's success.
#DesignEnablement
Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must possess a BS degree with

4

+ years of experience or MS degree with

3

+ years of experience or PhD degree with

1

+ years of experience in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering or a related field.

5+ years of experience in

two

or more

of the following areas:

- Intel and/or external foundry process technology knowledge in advance nodes
- Exposure to layout, schematic entry using Cadence Virtuoso and Synopsys Custom Designer
- Development/support or handling of issues pertaining to DRC, LVS, antenna, density and fill on foundry process technology
-

Exposure to one or more EDA tools on fill related issues (Synopsys ICV, Cadence Pegasus, Siemens Calibre)
Preferred Qualifications:
- Experience and background in analytical problem-solving to identify the key requests and root-causing the issue.
Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location:

US, Oregon, Hillsboro Additional Locations: US, Arizona, Phoenix, US, California, Santa Clara Business group: As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A

Benefits:
We

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

https://www.intel.com/content/www/us/en/jobs/benefits.html

Annual Salary Range for jobs which could be performed in
US,

California:$123,419.00-$185,123.00

S

al

ary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

Similar Jobs (5)

Physical Verification Applications Engineer (Design Enablement)

locations

3 Locations

time type

Full time

posted on

Posted 12 Days Ago

Physical Design Applications Engineer (Design Enablement)

locations

3 Locations

time type

Full time

posted on

Posted 3 Days Ago

Physical Design (SD) Engineer

locations

US, California, Santa Clara

time type

Full time

posted on

Posted 12 Days Ago
Intel provides reasonable accommodation to applicants and employees. For more information on our Reasonable Accommodation process, please click here .
To view our candidate privacy notice, please click here .
Need to change your email address?

Click on the Cloud icon beside your email address in the upper right-hand corner and select "Account Settings".

Important Note regarding your email change:

Remember to check the inbox of the email address you just updated to verify and complete the change. Verification is required before your account is changed to reflect the new email address.
#J-18808-Ljbffr
Original job Applications Engineer Physical Design/Fill - (Design Enablement) posted on GrabJobs ©. To flag any issues with this job please use the Report Job button on GrabJobs.

This job is no longer accepting applications.

Scroll down below to view similar jobs .

icon no cv required No CV Required icon fast interview Fast Interview via Chat

Share this job with your friends

icon get direction How to get there?

icon geo-alt Santa Clara, California

icon get direction How to get there?
View similar Others jobs below

Similar Jobs in the US

GrabJobs is the no1 job portal in the US, connecting you to thousands of jobs fast! Find the best jobs in the US, apply in 1 click and get a job today!

Mobile Apps

Copyright © 2024 Grabjobs Pte.Ltd. All Rights Reserved.