ASIC/SOC DFT Engineer (Silicon Engineering)

ASIC/SOC DFT ENGINEER (SILICON ENGINEERING)

RESPONSIBILITIES:

• Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools


• Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems


• Running and evaluating scan insertion through synthesis tools and refining scan insertion recipe for maximum coverage


• Run ATPG(Automatic Test Pattern Generation) analysis to ensure quality scan chain construction and meeting basic coverage goals


• Run and debug non-timing and SDF annotated gate level simulations


• Creating ATPG content for use in post-silicon testing and validating that content through gate level simulation


• Collaborate with circuit physical design team, ATPG team and manufacturing team to facilitate high quality scan coverage in silicon

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering or computer science


• 1+ years of professional experience working with ASICs


• Experience in scan insertion or DFT setup

PREFERRED SKILLS AND EXPERIENCE:

• Understanding of ASIC design flow, methodologies, physical design, and verification


• Experience with high reliability design and implementations


• Good scripting skills (csh/bash, Perl, Python etc.)


• Familiar with implementation or integration of design blocks using Verilog/SystemVerilog


• Familiar with UPF (unified power format), formal verification, and DRC rule checking experience


• Ability to work in a dynamic environment with changing needs and requirements


• Team-player, can-do attitude, and ability to work well in a group environment while still contributing on an individual basis


• Enjoys being challenged and learning new skills