Automotive HW Methodology Principal Engineer

## \nCompany:\n\nQualcomm Technologies, Inc.\n\n## Job Area:\n\nEngineering Group, Engineering Group \u003e ASICS Engineering\n\nGeneral Summary:\n\nDefine and drive end\u2011to\u2011end Predictive Maintenance solutions for automotive SoCs, spanning hardware architecture, DFT infrastructure, software enablement, and silicon reliability. The role requires strong SoC architecture experience and a deep understanding of the silicon development lifecycle, from early architecture definition through implementation, validation, qualification, and production. The position works across multiple domains and teams to ensure Predictive Maintenance capabilities are architected, implemented, and productized as part of automotive SoC platforms.\n\nRoles and Responsibilities\n\n * Architect and own Predictive Maintenance solutions across hardware, DFT, software, and reliability domains for automotive SoCs.\n\n * Drive SoC\u2011level architecture decisions to enable silicon health monitoring, aging prediction, and proactive failure mitigation.\n\n * Collaborate closely with SoC architecture, DFT, reliability, manufacturing, technology, and software teams throughout the full silicon development cycle (architecture, design, validation, qualification, and production).\n\n * Translate reliability and safety requirements into concrete hardware, DFT, and software mechanisms.\n\n * Influence methodology, infrastructure, and roadmap decisions to ensure scalable and reusable Predictive Maintenance solutions across automotive programs.\n\n * Collaborate with academic partners to explore and develop future models and data analysis techniques.\n\n * Represent Predictive Maintenance and silicon health topics in architecture reviews, safety reviews, and cross\u2011functional technical forums.\n\n\n\n\nMinimum Qualifications:\n\n\u2022 Bachelor\u0027s degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience. \nOR \nMaster\u0027s degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience. \nOR \nPhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.\n\nPreferred Qualifications:\n\n * Strong SoC architecture experience with a solid understanding of the full silicon development lifecycle (architecture definition through production).\n\n * Broad cross\u2011domain knowledge spanning hardware design, DFT/test infrastructure, firmware/software interaction, and system\u2011level reliability.\n\n * Experience with DFT technologies such as MBIST, ATPG, LBIST, in\u2011system test, and structural test reuse.\n\n * Good understanding of silicon aging, reliability mechanisms, and automotive qualification expectations (e.g., lifetime, availability, AEC\u2011Q100).\n\n * Understanding of AI/ML models and data analysis techniques.\n\n * Proven ability to drive cross\u2011functional technical solutions in complex, matrixed engineering organizations.\n\n * Automotive or other safety\u2011critical SoC experience is highly desirable.\n\n\n\n\nPrincipal Duties and Responsibilities:\n\n\u2022 Leverages expert ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products.\n\n\u2022 Creates highly advanced architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.\n\n\u2022 Collaborates with high-level representatives across functional teams (e.g., software architecture, hardware architecture, product management, program management teams) to develop and execute an implementation strategy that meets system requirements and customer needs.\n\n\u2022 Serves as an expert resource for all aspects of the process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.\n\n\u2022 Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable highly advanced architecture and design of multiple complex blocks/SoC or IC Packages; provides technical expertise and support to team members.\n\n\u2022 Writes detailed technical documentation for highly complex EDA/IP/ASIC projects; reviews technical documentation for experienced engineers.\n\nLevel of Responsibility: \n\u2022 Decision-making is critical in nature and highly impacts program, product, or project success. \n\u2022 Requires verbal and written communication skills to convey highly complex and/or detailed information. May require strong negotiation and influence with large groups or high-level constituents.\n\n\u2022 Has a great degree of influence over key organizational decisions (e.g., is making or directly making key decisions that will have substantial impact over the organization).\n\n\u2022 Tasks often require multiple steps which can be performed in various orders; extensive planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nQualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [email protected] or call Qualcomm\u0027s toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nEEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nPay range and Other Compensation \u0026 Benefits: \n\n$192,000.00 - $288,000.00\n\nThe above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer \u2013 and you can review more details about our US benefits at this link.\n\nIf you would like more information about this role, please contact Qualcomm Careers.\n