$175,000 - 400,000 yearly
About the job
Locations: Austin, TX | Chicago, IL | New York, NY | Boulder, CO
We're partnering with a leading technology-driven trading firm that designs high-performance compute platforms used in real-time production environments. Their hardware organization develops custom FPGA and ASIC solutions that directly power low-latency trading systems operating at massive scale.
The team is seeking Design Verification Engineers with strong SystemVerilog/UVM and Python experience who want meaningful ownership over verification methodology, automation, tooling, and infrastructure. You'll work closely with hardware designers to ensure the correctness and robustness of critical systems operating under demanding performance constraints.
This is a highly collaborative engineering environment where verification engineers are given significant ownership over methodology, infrastructure, tooling, and verification strategy rather than simply executing pre-defined test plans. Team members help shape verification frameworks, improve tooling, drive coverage closure, and contribute to the overall development process.
What You'll Do
What We're Looking For
Career Growth
The team is hiring individual contributors ranging from early-career engineers to experienced senior engineers. Candidates with leadership backgrounds are welcome, though this position is currently structured as a hands-on technical IC role rather than a people-management opportunity.
Compensation
Competitive base salary, annual performance bonus, and comprehensive benefits package. Compensation is highly dependent on experience, technical depth, and location.

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