Design Verification Engineer

icon briefcase Job Type : Full Time

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Job Description - Design Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

AMD together we advance_

THE ROLE:
The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s SOC devices, resulting in no bugs in the final design.
THE PERSON:
You have a passion for modern, complex SOC architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/

time zones

. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
Build the directed and random verification tests
Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements
Will

work as a member of a cross geographic pre silicon verification team to verify next generation SOC devices.
Will be responsible for regression, verification infrastructure development
PREFERRED EXPERIENCE:
Proficient in IP level ASIC verification, SOC verification experience is a plus
Proficient in debugging firmware and RTL code using simulation tools
Proficient in using UVM testbenches and working in Linux and Windows environment

s
Experienced with Verilog, System Verilog, C, and C++
Developing UVM based verification frameworks and testbenches, processes and flows
Strong background in the C language, preferably on Linux
Good understanding and hands-on experience in the UVM concepts and

SystemVerilog

language
Scripting language experience: Perl, Ruby,

Makefile

, shell preferred.
Exposure to leadership or mentorship is an asset
Good problem solving skills and attention to detail

.
Excellent written and verbal communication skills
ACADEMIC CREDENTIALS:
Bachelors or

Masters

degree in computer engineering/Electrical Engineering
LOCATION: San Jose, CA
#LI-DW1
#HYBRID

At AMD, your base pay is one part of your total rewards package. Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail

here .
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

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