Design Verification Engineer, DRAM

Contribute to the development of new product opportunities through design, layout, and optimization of Memory/Logic/Analog circuits. Fully understand the design datasheet. Study and learn the circuit design in detail. Understand the functionality and timing requirements of the circuitry. Develop patterns and regressions to increase the function coverage for all DRAM architectures and features. Provide support to design engineers, debug failures, lead bug tracking, and close coverage. Co-work with international colleagues on developing new verification tools and flows to solve the verification difficulties. Own and lead design projects and mentor junior engineers Develop and maintain test benches and test vectors using digital and analog simulation tools. Create new methods and flows to guide DRAM chip design from verification view. Create verification plan from functionality specification and in coordination with architects. Bachelor's degree in Electrical or Computer Engineering or equivalent. Basic understanding of CMOS circuit design Experience in mixed signal verification Familiar with analog/digital simulation tools, ie. HSPICE, VerilogHDL, FINESIM Knowledge and experience in verification languages (System Verilog or equivalent) and methodologies (UVM or equivalent) and other scripting languages (python, perl, etc). Good debugging and problem-solving skills Strong communication skills with the ability to convey sophisticated technical concepts to other verification peers. Experience with SystemVerilog Assertion (SVA) Strong leadership skills and attitude Bachelor's degree in Electrical or Computer Engineering and 2+ years of related experience. Master's degree in Electrical or Computer Engineering Exposure to cross-functional collaboration in a semiconductor environment. Knowledge of memory product development and validation workflows.