DFT Engineer

Job Title:
DFT Engineer (ATPG | SoC/ASIC | MBIST) 

Location: Santa Clara, CA (Onsite)

We are seeking experienced DFT Engineers with 5+ years of hands-on experience in Design for Test (DFT) and ATPG for SoC/ASIC designs. The ideal candidate will have strong expertise in scan-based testing, MBIST, IO testing, clock DFT, digital design, and RTL fundamentals, along with experience using industry-standard DFT/ATPG EDA tools. This is an onsite contract opportunity in Santa Clara, CA, supporting cutting-edge semiconductor programs in a fast-paced, high-performance environment.

Required Skills

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  5+ years of hands-on experience in DFT and ATPG for SoC/ASIC designs

  
  


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  Strong understanding of DFT fundamentals, including controllability, observability, and scan-based testing

  
  


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  Experience with ATPG pattern generation, analysis, and debug

  
  


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  Hands-on experience with MBIST architecture, implementation, and diagnostics

  
  


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  Knowledge of IO Test methodologies and pin-level validation

  
  


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  Experience with Clock DFT and clock verification

  
  


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  Strong understanding of Digital Design and RTL fundamentals

  
  


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  Experience using industry-standard DFT/ATPG EDA tools

  
  


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  Excellent debugging, analytical, and problem-solving skills

  
  

Qualifications

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  Bachelor's degree in Engineering (BE/B.Tech or equivalent)