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Lumotive is pioneering the era of programmable optics—where light is controlled as intelligently and flexibly as software.
At the heart of this transformation is a once-in-a-generation innovation: a flat CMOS-based “general purpose optic.” Lumotive’s Light Control Metasurface (LCM™) beam forming chips can be programmed to function as a beam steering mirror, a lens, mirror, a beam splitter—or any optical function—replacing bulky and mechanical optical components with a fully digital, reconfigurable semiconductor . This breakthrough lays the foundation for a massive shift in multiple technologies—from 3D sensing and imaging to optical networking, free space optical communication, and beyond. Like the shift from analog to digital in electronics, programmable optics will reshape industries from robotics, self-driving cars, AI, defense, and healthcare.
Lumotive’s first commercial application is in LiDAR, where its software-defined beam steering chips are already enabling compact, high-performance, solid-state sensors. These sensors are being deployed today in smart infrastructure, robotics, and mobility systems through leading module makers and solution integrators.
With more than 200 patents and growing commercial traction, Lumotive is delivering the world’s first digital platform for light—and redefining what’s possible in the optical age.
Job Description:
We are seeking a motivated and talented Entry-Level ASIC Design Engineer to join our growing mixed signal ASIC engineering team. This is an excellent opportunity for recent graduates passionate about digital or mixed-signal design to gain hands-on experience in the full lifecycle of ASIC development.
Responsibilities:
- Assist in the design and development of digital and/or mixed-signal ASIC blocks.
- Write RTL code using Verilog/SystemVerilog and simulate using industry-standard tools.
- Support functional verification and validation at the block and full-chip level.
- Collaborate with senior engineers across design, verification, DFT, physical design, and firmware teams.
- Perform synthesis, linting, timing analysis, and support bring-up/debug of first silicon
- Document design specifications and participate in design reviews.
Qualifications:
- BS or MS in Electrical Engineering, Computer Engineering, or related field
- Academic or project experience with ASIC/FPGA design flows
- Proficiency in Verilog or SystemVerilog
- Familiarity with EDA tools such as ModelSim, VCS, Synopsys, or Cadence
- Understanding of digital logic fundamentals, finite state machines, and timing analysis
- Strong analytical and debugging skills
- Excellent communication and team collaboration skills
- Exposure to mixed-signal or analog/digital co-design
- Experience with scripting languages (Python, TCL, Perl)
- Knowledge of industry-standard interfaces (SPI, I2C, AXI, etc.)
- Internship or academic project related to ASIC, SoC, or FPGA development
$90,000 - $110,000 a year
Base pay is scaled depending on experience + Performance based Quarterly Bonus + Equity.
Benefits include but not limited to:
Health, dental and vision
FSA, HSA
PTO plus 14 paid company holidays
401K with 3% contribution
Stock Options
Life insurance and disability
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