Engineer, DRAM DEVICE & CELL TECHNOLOGY

Develop understanding of process and device requirements for current and future DRAM memory cell and access device technologies and help establish electrical specifications. Characterize the memory array and model cell device and access device properties to identify improvement opportunities for yield, quality, and cost metrics. Contribute to the cell material and process flow definition. Understand and develop physical and electrical models for fundamental yield-limiting mechanisms in DRAM technologies through statistical data analysis of experiments conducted in semiconductor fab. Evaluate in-line, probe, parametric, and back-end data. Devise and implement experiments and stress tests to evaluate DRAM memory cell and access device capabilities and properties and the effects on reliability, functionality, and performance. Evaluate memory management and ECC to improve product quality and reliability metrics for current and future generations of DRAM memories. You have a detailed knowledge of mainstream memory technologies such as DRAM, NAND, NOR, & SRAM acquired through significant industry experience. Ability to characterize DRAM memory arrays on bench and other platforms to identify fail modes and guide process development. Expertise in device physics. You are very familiar with both Process Integration & Circuit/Architecture issues as they relate to memory. You are proficient with data analysis, DOE, and statistical techniques (JMP, Python). Education: MS (+ 5 years of experience) or PhD with hands research work or equivalent experience in Electrical Engineering, Physics, or other related technical field is required. Good written and verbal communication skills required. Excellent problem-solving, analytical, organizational, and team building skills Ability to provide project status updates to the team and management at a regular cadence. Experience demonstrating ability to collaborate effectively with multi-functional teams, including product, modeling, design & process integration engineers, to address cell deficiencies and implement improvement roadmaps.