HBM Memory Subsystem Architect MTS/SMTS/DMTS

Develop innovative memory subsystem frameworks for HBM solutions supporting AI/ML workloads, including PHY, controllers, NOC, microcontrollers, MBIST, interfaces, and adapters. Define Memory and RAS architecture requirements and drive architectural planning for next‑generation memory subsystems. Collaborate with internal and external partners to develop novel architectures and detailed IP requirements. Lead engagement with IP vendors, including evaluation and selection of interface and functional IP. Analyze benchmarks, workloads, and simulations to identify opportunities for performance, efficiency, and architectural innovation. Model performance, performance/watt, gate count, power, and area; create architectural and external‑facing specifications aligned with protocol and hardware standards. Partner with RTL, validation, and product teams to ensure timely and successful implementation, participating in design reviews for HBM and memory subsystem features. Drive microarchitecture definition, participate in performance simulation and benchmarking, and debug issues across models, RTL, and IP. Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Minimum of 15 years of experience in memory subsystem architecture and design. Deep understanding of memory controller design and memory types (DDR, LPDDR, GDDR, HBM). Experience with PHY design and understanding of signal integrity issues. Proficiency in Network-on-Chip (NoC) architecture and design. Familiarity with industry-standard bus protocols such as AXI, AMBA, AHB, DFI, etc. Strong analytical and problem-solving skills Excellent written and verbal communication skills PhD or equivalent experience in a relevant field Familiarity with EDA tools for design and verification Practical experience with multi-core systems, coherent interconnects & Industry IO protocol like PCIe/CXL, confidential compute, virtualization & security Knowledge of serial link protocols (UCIe etc.) is desired