Layout Engineer

About Ceragon:

Ceragon (NASDAQ: CRNT) is the global innovator and leading solutions provider of end-to-end wireless connectivity, specializing in transport, access, and AI-powered managed & professional services. Through our commitment to excellence, we empower customers to elevate operational efficiency and enrich the quality of experience for their end users.

Our customers include service providers, utilities, public safety organizations, government agencies, energy companies, and more, who rely on our wireless expertise and cutting-edge solutions for 5G & 4G broadband wireless connectivity, mission-critical services, and an array of applications that harness our ultra-high reliability and speed. Ceragon solutions are deployed by more than 600 service providers, as well as more than 1,600 private network owners, in more than 130 countries.

Through our innovative, end-to-end solutions, covering hardware, software, and managed & professional services, we enable our customers to embrace the future of wireless technology with confidence, shaping the next generation of connectivity and service delivery. Ceragon delivers extremely reliable, fast to deploy, high-capacity wireless solutions for a wide range of communication network use cases, optimized to lower TCO through minimal use of spectrum, power, real estate, and labor resources - driving simple, quick, and cost-effective network modernization and positioning Ceragon as a leading solutions provider for the “connectivity everywhere” era.

We are currently looking for a Senior Layout Engineer with more than 5 years of experience in analog/mixed-signal and RF layout. The core of this role is hands-on layout editing in RFIC development, responsible for turning schematic intent into verified, production-ready layout.

What you’ll do:

• Edit and finalize physical layout for analog and RFIC blocks, based on schematic plans, and prepare for tape-out and production.
• Perform placement, routing, and physical verification (DRC, LVS, ERC) using Cadence tools.
• Collaborate closely with design engineers to optimize layout vs. performance, parasitics, and area.
• Use your experience in SiGe BiCMOS and CMOS layout to deliver high-quality, manufacturable designs.
• Install and manage PDKs (Process Design Kits) in the Cadence environment, ensuring proper integration and tool flow stability.
• Support layout-related IT activities, including model installation and environment configuration.
• Contribute to design flow improvements, layout guidelines, or basic automation (optional).

What we're looking for:

• 5+ years of experience in analog/mixed-signal IC layout.
• Proven hands-on experience with SiGe BiCMOS and CMOS technology nodes.
• Strong command of Cadence Virtuoso and physical verification tools (e.g., Calibre, Assura).
• Experience with PDK installation and setup in Cadence tools.
• Solid understanding of design rules, and device matching principles.
• Attention to detail, ownership mindset, and strong collaboration skills.
• Fluency in English (written & spoken).

What we offer:

• Work in a global telecom company driving 5G and wireless innovation.
• Hybrid work model (2 days/week in office)
• Private medical insurance
• Meal tickets
• TOL reimbursement
• Opportunity to work in cross-functional teams with international exposure.
• Supportive, inclusive work culture focused on continuous improvement.

If you feel you’re the right candidate for the role, please click ‘apply’ now and send us your CV in English! We’d love to hear from you!