MTS Circuit Design Engineer, HSIO

Architect high-speed clocking networks for HBM applications in AI and HPC. Evaluate PLL performance and minimize sources of clock jitter and timing variation. Establish timing budgets and analyze clock path integrity. Contribute to effective project management and technical communication. Support layout-aware design decisions impacting speed, capacitance, power, and area. Ensure physical verification and quality of custom layout. Participate in multiple tape-out cycles and post-silicon validation. 10+ years of experience in analog/mixed-signal development. Master's degree in Electronic or VLSI Engineering preferred. Expertise in CMOS signal integrity and advanced process technologies. Strong understanding of analog layout fundamentals and parasitic effects. Proven ability to implement high-quality layouts under complex design constraints. Excellent verbal and written communication skills. Strong problem-solving skills in physical verification and debug. Experience with DRAM product bring-up and advanced packaging (TSV, hybrid bonding, interposers).