MTS Design Engineer, HBM

Design and optimize digital and analog DRAM circuits—including memory core circuits, sense margins, array timings, and die‑size efficiency—based on device specifications. Create and refine circuit floorplans to optimize placement, routing, parasitic behavior, signal integrity, and power delivery. Perform DRAM circuit verification using SPICE and Verilog, analyzing power, performance, reliability, and layout parasitics to ensure accurate circuit operation. Support DRAM silicon validation, debug, and correlation activities, identifying schematic edits and driving reticle experiments and necessary tape‑out revisions. Prepare detailed design documentation, contribute to critical design reviews, share best-known practices, and participate in team technical forums. Collaborate with Product Engineering, Test, Probe, Process Integration, Assembly, CAD, and Marketing to support manufacturability, qualification, and product success. Manage project activities including resource allocation, issue resolution, schedule tracking, and preparing status reports for management. Mentor engineers, support recruiting and interviewing, and lead design reviews to ensure project alignment and high‑quality design decisions. BS with 8+ years or MS with 5+ years of experience in circuit design, VLSI, or related technical fields. Coursework in CMOS circuit design, VLSI, and analog circuit design. Proficiency in Cadence Virtuoso and experience simulating with HSPICE and Verilog. Strong understanding of physical layout, circuit floorplanning, and device reliability. Excellent analytical, problem‑solving, and debugging skills. Experience in DRAM, HBM, or other memory circuit design and validation workflows. Experience supporting reticle experiments, silicon correlation, and tape‑out revision cycles. Proven ability to mentor engineers, contribute to build reviews, and support multi-functional collaboration.