MTS IO Design Architect, HBM

Define design targets and develop specifications for IO architecture Architect IO, clocking, and datapath for HBM products Plan IO development for next-generation products Collaborate with Product Engineering to correlate silicon measurements and simulations Ensure design quality through engagement with Standards, CAD, modeling, and verification teams Drive innovation for future memory generations Contribute to cross-group communication for standardization and success Perform optimization and verification of IO circuits MS or PhD in Electrical Engineering Minimum 10+ years of relevant engineering or design experience Expertise in high-speed clocking design at 16Gbps+ Strong knowledge of IO design principles and trade-offs (speed, area, power, complexity) Familiarity with off-chip protocols (UCIe, HBM, DDR, PCIe, MIPI, etc.) Hands-on experience with FinFET device characteristics Prior circuit debug experience through Product Engineering or equivalent Deep understanding of signal integrity, channel characteristics, and ESD design techniques