New College Grad - CAD/Computer Engineer, Central Engineering

Develop physical verification tools, flows, and methodologies for next‑generation DRAM, HBM, and emerging memory designs. Build, maintain, and validate DRC/LVS rule decks; guide design teams on physical verification procedures and checks. Collaborate with design, layout, verification, modeling, and process teams to define and implement product development and verification strategies. Evaluate and integrate EDA industry offerings (e.g., Cadence, Calibre) to improve quality, throughput, and efficiency. Debug and enhance in‑house and commercial EDA tools and automation for layout and verification workflows. Document standards, develop automation scripts, and contribute to continuous improvement of CAD/EDA processes. Bachelor's or Master's degree (or equivalent experience) in Computer Science or Computer Engineering. Strong Python programming fundamentals; ability to write clean, maintainable code for EDA automation. Unix/Linux proficiency; experience with shell scripting. Clear, concise communication skills and demonstrated problem‑solving ability. Growth mindset with an ambitious drive to learn, develop new skills, and self‑improve. Direct experience developing DRC/LVS rule decks and physical verification flows. Knowledge of CMOS circuit design, layout, and verification principles. Hands‑on experience with IC design CAD tools (schematics, layout, simulation, verification). Familiarity with Cadence (Virtuoso/Innovus) and Calibre (DRC/LVS) EDA tools. Experience supporting production EDA environments and collaborating with multi-functional silicon teams.