New College Grad - Layout Engineer

Create layout designs from floorplan through final implementation, ensuring alignment with schematic intent and process rules. Perform layout verification tasks, including DRC, LVS, and other quality checks. Collaborate with Design, Process Integration, and CAD teams to implement custom digital, memory, analog, and standard‑cell circuits. Integrate automated layout solutions and contribute to improvements in methods, automation, and documentation. Coordinate with local and global partners to deliver predictable, on‑time cell‑level layouts. Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent experience, or graduation from a layout school with a solid understanding of semiconductor processes. Familiarity with layout tools and methodologies, including Cadence Virtuoso VXL and Calibre for DRC/LVS/verification. Exposure to custom, logic, or analog semiconductor layout. Early‑career or new college graduate Layout Engineer with less than 2 years of custom, memory, or analog layout experience. Scripting experience (SKILL, Python) for methodology or automation development. Strong collaboration and written documentation skills. Understanding of CMOS processes, design rules, and layout‑dependent effects. Demonstrated problem‑solving skills with attention to detail and quality.