New College Grad - Semiconductor Design Engineer, DRAM Products Group

Assist with gate‑level to full‑chip design, layout, and performance optimization of memory circuits. Complete circuit simulations using industry‑standard tools such as SPICE and Verilog; debug and analyze results. Design and develop schematic blocks including memory arrays, control logic, address decode, datapaths, and internal test logic. Evaluate architectural tradeoffs and understand impacts on power, performance, area, and reliability. Import and analyze layout parasitics within circuit simulation environments; optimize design rules for cost and functionality. Interpret device specifications and translate them into die‑level circuit functionality across operating ranges. Support test chip definition, silicon validation strategies, and lab correlation efforts. Collaborate with Product Engineering, Test, Probe, Process Integration, Assembly, and Marketing to ensure manufacturability. Find opportunities to introduce innovative concepts that deliver competitive advantages. Bachelor's degree in Electrical Engineering or higher. Basic understanding of memory applications and CMOS device behavior. Strong foundation in circuit simulation setup, analysis, and debug. Effective written and verbal communication skills with the ability to convey complex technical concepts. Experience with memory circuit design and layout optimization. Familiarity with reliability limits of CMOS processes. Exposure to silicon validation and test chip bring‑up. Demonstrated motivation to grow technically and contribute within collaborative, global teams.