Power Methodology Lead

We are seeking a Power Methodology Lead for high-performance designs going into industry leading CPU and AI/ML architecture. The person coming into this role will translate power requirements and constraints from architecture and RTL teams into physical design specifications. The work is done alongside with a group of highly experienced engineers across various domains of the CPU/AI chip.

This role is hybrid, based out of Santa Clara, CA, Austin, TX or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities:

• Collaborate with the Architecture and RTL team to deliver power-efficient, high-performance chips.


• Translate power requirements and constraints from architecture and RTL teams into physical design specifications.


• Lead the adoption of power optimization techniques (including clock gating, power gating, and multi-voltage) across architecture, RTL, and Physical Design teams.


• Propose and implement power physical design techniques to minimize power consumption while meeting performance and area targets.


• Evaluate and benchmark new power analysis and optimization tools and methodologies.


• Stay current with the latest industry trends and advancements in power VLSI design and physical implementation.

Experience & Qualifications:

• BS/MS/PhD in EE/ECE.


• Strong background and experience with high-performance/low-power designs.


• 10+ years of experience in VLSI physical design with a strong focus on power methodology and implementation.


• In-depth understanding of power intent specification formats (UPF/CPF) and their application in physical design


• Experience with verifying the power intent using industry standard tools like VCLP and Conformal LP


• Solid knowledge of power grid design principles and power integrity analysis (IR drop, EM).


• Hands-on experience with industry-standard physical design tools (e.g., Cadence Innovus, Synopsys IC Compiler) and power analysis tools (e.g., Ansys RedHawk, Cadence Voltus, Synopsys PrimePower).


• Proficiency in scripting languages (Python, Perl, TCL) for automation and flow development.


• Strong problem-solving and debugging skills.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government.

Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process.

If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.