Principal Analog/Mixed Signal Engineer

Principal Analog/Mixed Signal Engineer

Company: Extropic
Location: Boston, MA (hybrid, 3 days in office)
Compensation: $200,000 - $325,000 + competitive equity
Employment Type: Full-time
Visa Sponsorship: Visa transfers and new sponsorship (H-1B, TN)

About Extropic

Extropic is building thermodynamic computing, a new compute paradigm that uses thermal noise in CMOS devices to perform probabilistic computation with radical power efficiency (potentially 10,000x savings over traditional approaches). Its founders, former Google Quantum Computing researchers, spent years fighting thermal noise before realizing they could harness it.

Founded in 2022, Extropic has about 30 people, has taped out its third chip (Z1) and is defining the architecture for three more. It has raised a $14.1M seed.

The Role

Extropic is hiring a Principal Analog/Mixed Signal Engineer (6+ years) to lead the design of next-generation thermodynamic computing chips. This is a ground-floor chance to own major pieces of chip design, and potentially serve as design lead for one of three planned chips, at a company positioned to reshape AI acceleration and edge computing.

What You Will Do

• Lead design of analog and mixed-signal blocks: ADCs, PLLs, bandgaps, regulators, high-speed SerDes, oscillators and dividers.
• Own large parts of chip architecture, potentially as design lead for an upcoming chip.
• Do hands-on layout and design verification (DRC, ERC, LVS).
• Work across IC, systems, physics and algorithms teams to turn probabilistic computing concepts into silicon.
• Test and validate fabricated chips in the lab with signal generators, spectrum analyzers and oscilloscopes.

What You Bring

• 6+ years of analog/mixed-signal IC design
• Block design experience (ADCs, PLLs, SerDes, bandgaps, regulators)
• Hands-on layout and verification (DRC, ERC, LVS) in Cadence
• CMOS and FinFET process experience
• Lab bring-up and validation skills
• Ability to work hybrid 3 days a week in Boston

Tech Stack

CMOS, Cadence, FinFET, PLL, ADC, SerDes, Python, C

REVENUE: 20% of first-year salary. Est. fee per hire $40K-$65K; 2 seat(s) = up to $105K if all filled.

TARGET COMPANIES (suggested): Apple, Qualcomm, Analog Devices, Texas Instruments, Broadcom, Intel.

BEST-FIT CANDIDATE: 6+ yrs; analog/mixed-signal IC blocks; Cadence layout + verification; tapeouts; visa: transfers + new H-1B/TN; location: Boston hybrid 3 days.