Principal Design Engineer, DRAM

Design and optimize memory circuits from gate‑level to full chip implementations. Lead development of schematic blocks such as memory arrays, control logic, address decode, datapath, and internal test logic. Perform advanced circuit simulations using industry tools (e.g., SPICE, VERILOG) to validate performance. Drive architectural decisions related to power, speed, die area, and overall circuit performance. Collaborate with technology development and business units to define design rules, device requirements, and validation strategies. Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field (or equivalent practical experience). Experience in semiconductor circuit design, layout, and optimization. Proficiency with circuit simulation and design tools such as SPICE and VERILOG. Demonstrated ability to interpret product requirements, logic diagrams, and device specifications. Experience evaluating and modifying semiconductor devices and components. Master's degree or PhD in Electrical Engineering or a related discipline. Experience leading sophisticated circuit design projects or technical teams. Background in memory architecture, CMOS device behavior, and reliability considerations. Experience defining test chips and supporting silicon validation. Proven track record of innovation in circuit design or semiconductor technology.