Principal Design Engineer, NVEG

Manage major IO/datapath block(e.g. input receiver, serializer, deserializer, clock distribution, equalizer, ZQ calibration, ONFI training features, wave pipeline) to meet specifications and verify functionality and performance Model parasitics on layout and optimize signal quality by layout optimization. Review layout regularly and find opportunities of improving area/power. Communicate with project integration and other functional teams in design on specifications of major block interfaces Communicate with PE to drive silicon experiments and propose and implement fixes for yield improvement and silicon debugging Communicate with Apps regarding introduction of new specs and limitations based on design requirements and limitations Document and review final results with experts and stakeholders BS or MS in Electrical Engineering with 8+ years of relevant experience Experience in physical design flows and optimization, top-level IO blocks floorplan, and high-speed interfaces for NAND and training features Advanced knowledge and understanding of high-speed IO circuit performance, power and area optimization, and chip architecture/floorplan Experience with managing complex design projects, effectively communicating progress and outcomes Hands-on experience in utilizing AI to improve quality of design and efficiency Experience in DRAM interface (e.g. DDR4/5, LPDDR5/6, HBM3/3E/4) as well as other industry standard interfaces Experience in chip level PDN optimization, signal/power integrity, power delivery network design, and physical design Comprehensive understanding of CMOS BSIM model, CMOS targets for high speed IO operation, and CMOS device reliability