Principal Systems Design Engineer, HBM

Own full-chip floorplanning, design partitioning, and top-level synthesis with multiple hard macro IP blocks. Develop automated high-speed matching routing and ensure timely delivery of high-quality block-level layouts. Perform physical verification (LVS/DRC/Antenna), quality checks, and documentation support. Lead planning, estimation, scheduling, and execution across multiple projects. Guide junior team members in sub-block layout execution and review critical design elements. Collaborate effectively with global engineering teams to ensure layout project success. Understand layout effects on circuit performance (speed, capacitance, power, area). Contribute to project management and cross-functional communication. 10+ years of experience in analog/custom layout design across advanced CMOS nodes (Planar, FinFET). Proficiency in Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS. Hands-on experience with industry APR tools like Innovus or Fusion Compiler. Strong understanding of analog layout fundamentals and parasitic effects. Proven ability to implement high-quality layouts under complex design constraints. Excellent verbal and written communication skills. Strong problem-solving skills in physical verification and debug. Experience supporting multiple tape-outs and working with memory design hierarchies.