Process engineer

Design and develop advanced packaging architectures for microLED photonic interconnects and heterogeneous integration. Lead Cu backplane RDL design, layout, fabrication, and integration. Develop mass transfer and die bonding solutions, including thermal compression bonding and hybrid bonding, tailored to system integration requirements. Collaborate with substrate layout, IC design, and module teams to co-optimize packaging, signal integrity, and thermal performance. Perform thermal, mechanical, and optical simulations to validate packaging reliability and performance. Conduct optical, electrical, and tolerance analysis of photonic devices; optimize components for performance, efficiency, reliability, and manufacturability. Ph.D. in EE, MSE, Phys, or related discipline (M.S. with relevant experience may be considered). Proven experience in Cu RDL layout, design, fabrication, and integration. Hands-on expertise in thermal compression bonding and hybrid bonding processes. Experience with Co-Packaged Optics (CPO) and Optical Engine development. Experience working in cleanroom environments and advanced IC fabrication. Proficiency in design layout and simulation software such as Cadence (APD/SIP), AutoCAD, SolidWorks, KLayout, COMSOL and Ansys. Strong problem-solving skills and ability to work in a collaborative research environment.