Process Integration Engineer - DRAM, DMTS

In this role, you will need to have strong semiconductor Process Integration skills in an R&D department. You will be developing the future generation DRAM technologies. This is a career path for individuals seeking to advance as technical leaders and industry innovators. TLP members are expected to influence, lead, and mentor others. Define and implement BEOL process flows, build rules, and specifications for advanced DRAM products. Lead troubleshooting and resolution of complex integration issues spanning multiple modules and fields. Drive yield improvement and reliability enhancement initiatives using data-driven methodologies. Coordinate technology transfers, ensuring robust process qualification and rapid ramp to high-volume manufacturing. Engage in industry benchmarking and collaborative projects to maintain technology leadership. Pathfinding alternate architectures and enablers. Foster a culture of innovation, continuous learning, and operational excellence within the BEOL team. MS (required) or PhD or equivalent experience (preferred) in Electrical Engineering, Microelectronics, Materials Science, or a related area; along with more than 10 years of industry experience. Deep expertise in metallization, barrier/liner engineering, dielectric integration, and reliability solutions for next-generation DRAM nodes. Successful leadership of BEOL process development from R&D through pilot and high-volume manufacturing, including cross-node and cross-site technology transfers. Proficient in statistical data analysis and advanced problem-solving techniques. Strong leadership, communication, and project management skills. Recognized for creativity, adaptability, and a proactive approach to emerging challenges. Authored/co-authored multiple patents and technical papers on DRAM BEOL integration. PhD degree in Electrical Engineering, Microelectronics, Materials Science or a related area. 10+ years fo industry experience with next-generation DRAM nodes Technical leadership skills in an R&D setting