Lead Process Integration execution and readiness for assigned DRAM modules during tech transfer and early HVM Drive root‑cause investigations and yield improvement using DOE, SPC/FDC, FMEA, 8D, and structured problem solving Ensure process margin, manufacturability, and reliability requirements are met and sustained Manage and develop a team of PI engineers, providing coaching, priorities, and technical guidance Partner across Manufacturing, Equipment, Yield, Device, TD, Quality, and Design to drive alignment and resolve issues quickly Bachelor's degree and 5+ years experience in high‑volume manufacturing or semiconductor fab operations 5+ years experience with memory process technologies 5+ years experience in yield ramp, cost reduction, or quality improvement within semiconductor fabrication Proven experience in leading Process Integration teams Strong understanding of transistor operation, scaling limits, and reliability fundamentals Masters/PHD in Material Science, Electrical or other engineering areas Experience leading technology transfer or new product introduction activities Background supporting DRAM module integration during pilot and early HVM Familiarity with process window development, SPC/FDC strategies, and inter‑fab learning frameworks Working knowledge of CMOS processes and characterization methods
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