CPU Architect, Load-Store

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We are seeking a highly motivated and passionate CPU Architect to join our processor architecture team, focusing on the CPU’s load-store unit. In this role, you will contribute to the design, analysis, and optimization of cutting-edge CPU architectures with an emphasis on a high-performance load-store unit. This is an excellent opportunity to work alongside world class architects in high-performance computing and processor design.

This role is Remote, based out of The United States.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities:

• Drive the architecture, micro-architecture, design and optimization of the CPU load-store unit for Tenstorrent’s high-performance out-of-order RISCV CPUs


• Propose new implementations to optimize load-store PPA


• Perform simulations, modeling, and performance analysis of advanced CPU features and state-of-the-art data prefetchers


• Collaborate with hardware and software teams to optimize memory access patterns and system performance.


• Stay up to date with industry trends and emerging technologies in CPU architecture and the memory subsystem


• Support documentation and presentation of architectural decisions, trade-offs, and findings.

Experience & Qualifications:

• Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or Computer Science (or equivalent experience).


• Strong understanding of computer architecture fundamentals, including memory hierarchy, cache coherence, and data prefetching


• Familiarity with performance modeling and simulation tools (e.g., Gem5, SimpleScalar, or similar).


• Basic knowledge of hardware description languages (e.g., Verilog, VHDL) and system-level programming (C, C++).


• Problem-solving skills and ability to analyze complex system interactions.


• Excellent communication and teamwork abilities.


• Hands-on experience with performance profiling tools and benchmarking methodologies.


• Exposure to parallel processing architectures and multi-core systems.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government.

Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process.

If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.