Design Verification (DV) engineer

Position6 : Design Verification (DV) engineer

Location : Remote

Only USC/GC- W2

Experienced Design Verification (DV) engineer for an upcoming IP verification project.

Scope of Work:

• Development of a comprehensive verification plan based on hardware requirements.


• Design, integration, and maintenance of UVM-based testbench components.


• Development of constrained-random test cases, sequences, and assertion-based checkers.


• Application of AI-based verification methods and productivity tools where appropriate.


• Execution of verification plan and implementation reviews with our Digital Design and Concept teams.


• Coverage closure and detailed metrics analysis.


• Generation of formal verification reports and regular attendance at project alignment meetings.


• Development of a comprehensive verification plan based on hardware requirements.


• Design, integration, and maintenance of UVM-based testbench components.


• Development of constrained-random test cases, sequences, and assertion-based checkers.


• Application of AI-based verification methods and productivity tools where appropriate.


• Execution of verification plan and implementation reviews with our Digital Design and Concept teams.


• Coverage closure and detailed metrics analysis.


• Generation of formal verification reports and regular attendance at project alignment meetings.