Senior Design Engineer, HBM Base Design

Design and develop high-speed interface PHY and sub-blocks (e.g., calibration, training, loopback, clock domain crossing). Convert architecture specifications into micro-architecture and implement logic in RTL (Verilog/SystemVerilog). Perform formal and functional verification of designs. Collaborate with multi-functional teams (Product Engineering, Test, Probe, etc.) to improve manufacturing and performance. Debug and root-cause RTL simulation, silicon, and system failures. Interface with analog, modeling, and APR designers for seamless integration. Write scripts to automate design tool flows and improve efficiency. Maintain technical expertise and provide training to peers. Bachelor's degree in Electrical Engineering or a related field, or equivalent experience. 5+ years of relevant engineering or design experience. Strong knowledge of digital design, Verilog, and scripting languages. Experience with micro-architecture and asynchronous digital designs. Familiarity with synthesis, STA, Lint, and CDC tools. Working knowledge of DDR/LPDDR JEDEC protocols and DDR PHY designs. Experience with DDR training algorithms and data path designs. Familiarity with domain transfer designs, APB/JTAG, and DFI.