Senior Design Verification Engineer

At Elevate Semiconductor, we empower semiconductor and system test customers by creating world class ICs that tackle the industry’s most complex automated test equipment challenges. Our innovative team designs the lowest power, highest density solutions to reduce cost of test while pushing performance forward.

Elevate Semiconductor is seeking a Design Verification Engineer to join our IC development team building high performance analog and mixed signal integrated circuits. In this role, you will own the verification lifecycle and play a critical role in ensuring first pass silicon success.

You will work closely with both analog and digital design teams to develop verification strategies, build robust verification environments, and validate complex mixed signal interactions across the chip. This role offers the opportunity to make a meaningful impact in a collaborative environment focused on innovation, precision, and execution.

Responsibilities

• Develop and execute verification plans for mixed signal IC designs based on product specifications
• Build advanced simulation test benches using randomized and rule based stimulus to verify functionality and performance
• Create Verilog AMS behavioral models of analog circuits to accelerate verification
• Verify analog and digital interaction at both the block and system level
• Develop functional and code coverage models and drive coverage closure
• Run gate level simulations, power verification, and formal verification when required
• Partner with analog and digital design engineers to define effective verification strategies and ensure coverage of critical corner cases
• Support post silicon validation and debug

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
• 5+ years of experience in mixed signal IC verification
• Strong understanding of mixed signal verification methodologies and design flows
• Experience developing verification environments and behavioral models
• Proficiency in SystemVerilog, UVM, and Verilog
• Experience with Verilog AMS and AMS simulation environments such as Spectre AMS Designer
• Experience with functional and code coverage methodologies
• Strong collaboration and communication skills

• 100% Employer Paid Health Insurance (Medical, Dental, Vision)
• Unlimited Paid Time Off
• Performance Bonuses
• Free Lunch Catered in by Local Restaurants
• Private Equity Options
• Retirement Plans
• Sabbatical Program
• Tuition Reimbursement
• Volunteer Days
• Relocation Assistance
• Conference Attendance Support
• Biweekly Phone Stipend
• Employee Assistance Program

The salary range for this role is $114,500.00 to $155,000.00. Starting salary will be aligned with your relevant experience and demonstrated capabilities during the interview process. Typically, candidates begin at the initial tier of our compensation range, with placement adjusted for candidates presenting extensive directly applicable experience.