Senior Distinguished Engineer, SerDes Receiver & ADC

About the Role

We are building a world-class SerDes engineering organization focused on next-generation, ultra-high-speed connectivity for AI data centers and high-performance computing.

We are seeking an exceptional technical leader to define and drive the architecture and implementation of next-generation SerDes receiver front ends and high-speed analog-to-digital converters (ADCs), targeting ultra-high sampling rates in advanced process technologies at 5nm and below.

This is a high-impact technical leadership role for an engineer who combines deep expertise in high-speed analog and mixed-signal circuit design with strong architectural judgment and a proven ability to turn ambitious performance targets into silicon.

As a key technical leader, you will shape receiver architecture, drive critical circuit and system-level trade-offs, and work across analog design, DSP, clocking, digital implementation, and silicon validation to deliver industry-leading receiver performance. You will have the opportunity to influence the technical direction of our SerDes platform and establish the foundation for future generations of high-speed connectivity.

Responsibilities: 

• Receiver Architecture: Define and drive the architecture of next-generation, ultra-high-speed SerDes receivers, including the analog front end, ADC, sampling architecture, clocking interfaces, and integration with digital signal processing.


• High-Speed ADC Development: Lead the design and optimization of ADCs targeting 100+ GS/s, addressing sampling speed, resolution, linearity, noise, power efficiency, and implementation complexity.


• Analog Front-End Design: Drive receiver front-end development, including high-bandwidth input stages, equalization, gain control, sampling networks, and other critical analog building blocks.


• Advanced-Node Implementation: Lead circuit design and implementation in 5nm and below technologies, leveraging advanced CMOS capabilities while managing device limitations, parasitics, variability, power integrity, and layout-dependent effects.


• System-Level Optimization: Establish architectural trade-offs across bandwidth, signal-to-noise ratio, effective number of bits (ENOB), jitter tolerance, power consumption, and DSP complexity to optimize overall link performance.


• Clocking and Sampling: Collaborate on clock generation and distribution, sampling-clock quality, aperture jitter, phase noise, and clock-to-data timing requirements at extreme sampling rates.


• Technical Leadership: Set technical direction, guide critical design decisions, mentor senior engineers, and drive resolution of complex circuit and system-level challenges.


• Cross-Functional Collaboration: Partner closely with TX, clocking, DSP, physical design, package, signal integrity, and silicon validation teams to deliver an integrated, high-performance SerDes solution.


• Silicon Execution: Drive feasibility studies, architectural modeling, circuit simulations, design reviews, silicon characterization, and performance correlation to ensure successful implementation and product delivery.


• Technology Roadmap: Shape the receiver technology roadmap and identify new circuit architectures and implementation techniques to extend the performance and energy-efficiency limits of future SerDes generations.

Qualifications:

• MS or PhD in Electrical Engineering or a related field, with extensive relevant experience in high-speed analog and mixed-signal IC design.


• Demonstrated expertise in high-speed SerDes receiver architecture and circuit implementation, including ADC-based receivers.


• Significant experience designing advanced CMOS circuits in 5nm or below process technologies.


• Strong hands-on understanding of high-speed ADC architectures and their practical implementation challenges, including sampling networks, comparator design, reference generation, calibration, linearity, noise, and clocking.


• Deep understanding of high-speed receiver performance metrics, including bandwidth, SNR, ENOB, jitter tolerance, equalization, and power efficiency.


• Proven ability to make architecture-level decisions informed by circuit-level analysis, system modeling, and silicon measurement.


• Track record of leading complex, high-performance analog or mixed-signal designs from architecture through tape-out and silicon validation.


• Excellent technical communication skills and the ability to influence design direction across multidisciplinary engineering teams.

Preferred Qualifications:

• Direct experience with 100G-per-lane or higher SerDes receiver development, including advanced ADC-based architectures.


• Experience developing ADCs with sampling rates approaching or exceeding 100 GS/s, or equivalent expertise in highly time-interleaved, multi-phase, or distributed sampling architectures.


• Expertise in ADC architecture trade-offs, including time interleaving, comparator and sampler design, calibration techniques, mismatch mitigation, and interleaving-spur reduction.


• Strong understanding of the interaction between analog front-end design, clocking, DSP algorithms, and channel characteristics.


• Experience with advanced packaging, chiplet-based systems, and high-bandwidth die-to-die or data center interconnect technologies. Recognized technical contributions through successful silicon products, patents, publications, or leadership in advanced SerDes and ADC development.