Collaborate with IP vendors, architecture, verification, physical design, and software teams to deliver robust PCIe subsystems. Develop and maintain firmware that adheres to PCIe specifications (Base, CEM, ECN). Develop test plans, testbenches, and simulation environments to verify PCIe functionality. Ensure compliance with PCIe specifications and participate in interoperability testing where needed. BS or MS degree in Electrical Engineering or related field. Minimum 5 years of experience in design, verification, and analysis of PCIe subsystems. Expertise in PCIe protocols and architecture (Gen4/Gen5/Gen6). Experience with high-speed serial interfaces including SerDes, PLL, and equalization techniques. Knowledge of Python or other scripting languages for automation of testing and analysis. Experience with other protocols such as USB, SATA, NVMe, or Ethernet.
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