Senior Memory Sustaining Design Engineer, HBM

Design, layout, and optimize Memory, Logic, and Analog circuits for HBM products. Support parasitic modeling, design validation, reticle experiments, and tape-out revisions. Collaborate with layout teams to meet floorplanning, placement, and routing goals. Simulate and verify designs using FineSim, HSPICE, and Verilog. Perform power delivery network analysis and optimization. Run design checks prior to initial and revision tapeouts. Drive innovation for future memory generations in a collaborative environment. Mentor new college graduate hires and engage cross-functionally with CAD, modeling, and verification teams. BS or MS in Electrical Engineering or related field. 5+ years (BS) or 3+ years (MS) of relevant experience. Strong CMOS circuit design skills and understanding of semiconductor device physics. Experience with schematic entry, Verilog, FastSpice, and HSPICE simulations. Solid grasp of timing/area/power/complexity trade-offs in DRAM or mixed-signal design. Strong verbal and written communication skills for conveying technical concepts. Self-motivated team player who thrives in diverse environments. Excellent problem-solving and analytical skills, with scripting experience (Python, TCL, Perl) and familiarity with RTL design flow in DRAM or Foundry processes.