Senior Principal ASIC DFT Engineer

Responsible for all aspects of DFT (Design for Test) for ASIC designs Responsible for defining the overall test strategy and test plan Responsible for developing DFT architecture and implementation, including scan, logic BIST, memory BIST and repair, hierarchical test, boundary scan, and ATPG Responsible for advanced DFT methodology and flow development Bachelor's degree with 8 years of experience, a Master's degree with 6 years of experience or a Ph.D. with 4 years of experience in Science, Technology, Engineering, Mathematics, or related technical fields; an additional 4 years of experience may be considered in lieu of a degree. Ability to obtain/maintain an active secret clearance Experience in full product life cycle of ASIC Design Experience with Cadence and/or Mentor test insertion and ATPG tools Experience with hierarchical scan testing, IEEE-1500 and/or IEEE-1687, test compression, JTAG IEEE-1149.1 and IEEE-1149.6 (AC JTA Experience with memory BIST and logic BIST Experience generating test patterns and analyzing and debugging test failures Experience working with test engineers to implement ATPG vectors on tester hardware Master's Degree in Electrical or Computer Engineering Knowledge of Synthesis, P&R and Static Timing Analysis would be a plus Active DoD Secret Clearance or higher