Job Description - Senior Principal Engineer, IC Physical Design
Senior Principal Physical IC Design Engineer
Location: Camarillo, CA (On-Site)
About SAAZ Micro
SAAZ Micro designs and manufactures advanced electro-optical and infrared semiconductor solutions spanning detectors, ROICs, ASICs, advanced packaging, and edge-AI systems for defense, space, and commercial markets. Our vertically integrated approach enables rapid transition from concept to deployed systems.
We are seeking a Principal Physical IC Design Engineer to lead physical implementation of complex mixed-signal and digital ICs across multiple technology nodes, working closely with architecture, circuit design, packaging, and manufacturing teams.
Role Overview
As a Principal Physical IC Design Engineer, you will own the full physical implementation flow for advanced ICs—from synthesis handoff through place-and-route, signoff, and tape-out. You will act as a technical authority on physical design tradeoffs involving performance, power, area, reliability, and manufacturability, and mentor other engineers while shaping best practices across the organization.
This is a hands-on technical leadership role, not a management position. The role may require supervision and mentoring of junior staff.
This is a full-time, on-site role at SAAZ’s Camarillo, California facility.
Key Responsibilities
Lead end-to-end physical design and implementation of complex digital and mixed-signal ICs
Floorplanning, power planning, placement, clock tree synthesis, routing, and optimization
Own timing closure, power integrity, signal integrity, EM/IR, and DFM signoff
Drive resolution of DRC, LVS, antenna, ESD, and reliability issues through tape-out
Work across a wide range of process nodes (≈350nm down to 7nm and below)
Interface closely with:
Digital RTL and verification teams
Analog and mixed-signal designers
Packaging and system engineers
Foundries and external design partners
Evaluate and optimize physical architectures for performance, power, yield, and scalability
Develop and maintain physical design methodologies, scripts, and flows
Mentor junior and senior engineers in physical implementation best practices
Support silicon bring-up, debug, and yield-learning activities post-tape-out
Required Qualifications
Bachelor’s or Master’s degree in Electrical Engineering or related field
10+ years of hands-on experience in physical IC design and implementation
Proven experience independently owning place-and-route through signoff
Strong understanding of ROICs, ASIC, 3D-ICs, cryo, rad-hard and stitched methodologies
Strong understanding of:
Timing analysis (STA)
Power delivery networks
EM/IR and reliability constraints
DRC/LVS/antenna/ESD rules
Experience with industry-standard EDA tools (e.g., Synopsys, Cadence)
Experience working across multiple standard-cell libraries and timing models
Demonstrated success taking multiple chips to silicon
Preferred Qualifications
Experience with mixed-signal or sensor-centric ASICs
Familiarity with advanced packaging or chip-to-chip integration
Experience working with aerospace, defense, or high-reliability silicon
US citizen who has held secret level or higher clearances
Ability to read and collaborate on RTL and analog layouts
Experience improving or building physical design flows from the ground up
Work Environment
On-site position at SAAZ’s Camarillo, CA facility
Close collaboration with silicon, systems, and packaging teams
Access to full-stack semiconductor development—from device to deployed system
Why SAAZ
Work on mission-critical sensors and ASICs used in real-world deployments
Influence architecture and silicon outcomes at the earliest design stages
Join a deeply technical, fast-moving team with real ownership and impact
Opportunity to shape the physical design strategy of a growing semiconductor company
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