SMTS Design Engineer, NVEG

Design key IO design building blocks (e.g. input receiver, equalizer, SerDes, Clock distribution circuits) to meet specifications and validate functionality and performance Model parasitics and optimize signal quality in close collaboration with layout teams Optimize circuit design based on a comprehensive understanding of CMOS technology and reliability Document and review final results with experts and stakeholders Maintain technical expertise, stay informed on industry trends, and provide training to the product validation team on design architecture and features Set individual objectives according to the team's growth and milestones, manage performance reviews, and help shape strategic decisions BS in Electrical Engineering, MS or PHD preferred Required 13+ years of relevant experience in the semiconductor industry working directly with memory product design Deep knowledge and understanding of high-speed IO circuits performance, power and area optimization, chip architecture/floorplan Demonstrated experience in leading and mentoring others to impact organizational effectiveness and knowledge-sharing Ability to convey complex technical concepts in verbal and written form; Patents and publications are a plus. Familiarity with full-custom EDA tools (e.g. cadence, hspice, XA, verilog), plus Python and Matlab for design flow automation Advanced expertise in physical design flows and optimization Ability to work effectively both as a collaborator and individual contributor Knowledge and understanding of SerDes, wave pipeline circuits 10+ years experience with signal/power integrity, power delivery network design, physical design Experience with post silicon activity such as providing training on product validation and implementing design fixes under constraints Experience with CMOS BSIM models and creating CMOS targets for IO roadmap 10+ years experience with high-speed interfaces for NAND as well as DRAM (e.g. LPDDR5/LPDDR6) and other industry standard interfaces Recognized contributions to industry standards, patents, and published technical papers