Sr Design Verification Engineer

Role:

• Develop and execute verification plans for units and features.
• Construct testbenches, scoreboards, and stimulus generators.
• Implement functional coverage models.
• Debug designs in simulation, prototyping platforms, and silicon.

Qualifications Required:

• Roles requiring both 4+ and 8+ years industry experience
• Bachelor’s or Master’s degree in related engineering field
• Ability to work independently and across geographies
• Strong domain knowledge of computer architecture

Skills and Qualifications Desired:

• SystemVerilog verification development experience
• Testbench construction using UVM or analogous methodologies
• Scoreboards and stimulus generators for complex units
• Industry experience with CPU microarchitecture (e.g. x86, ARM, SPARC, MIPS, RISC-V, POWER) and/or coherent caching systems
• Software development experience in compiled (C/C++) and interpreted (Python) languages
• Unit or feature ownership throughout the project lifecycle
• BASE SALARY RANGE
  
  $105,000 TO $260,000 per year

• EEOE

  Ventana is an Equal Employment Opportunity Employer. We value diversity and uphold an inclusive environment where all people feel that they are equally respected and valued. Qualified applicants will receive consideration without regard to race, color, creed, religion, sex, sexual orientation, national origin or nationality, ancestry, age, disability, gender identity or expression, marital status, veteran status, or any other category protected by law.

   COVID-19

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