Sr. DFX Technical Lead

Contribute to building of a world-class, brand new DFX team Work closely with EDA Vendors & CAD team to define next generation DFT flows and methodology with latest & greatest features Collaborate with cross site / geography teams to help establish great working relationship and deal very efficiently with deliverables across teams Contribute to building of a world-class, brand new DFX team Work closely with EDA Vendors & CAD team to define next generation DFT flows and methodology with latest & greatest features Collaborate with cross site / geography teams to help establish great working relationship and deal very efficiently with deliverables across teams 12+ years of experience (10+ years with MSEE) working at a senior level role in SOC/IP/ASIC design team with an emphasis around DFX (DFT/DFD/DFM) Must have expert level, working knowledge about DFX standards and practices, ATPG, Scan, JTAG, iJTAG, BIST, including trade-offs between test quality, test time, efficiency and their impact to overall design implementation Experience with SOC level DFT planning, architecture, and execution. Understanding of industry road map on DFX and active contributions towards improvements in DFX working with industry experts Good focus on automation & infrastructure to enable efficient execution pipeline within DFX function Experience with post silicon debug, yield bring up, test-time and pattern delivery while working closely with TEPE teams for long term strategic improvements Continuous drive to improve flows, methodology and architecture for enabling scalability of the overall team in years to come Understanding of Physical design implementation flows and methods to enable a smooth integration of DFT in the design with efficient and quality hand offs 12+ years of experience (10+ years with MSEE) working at a senior level role in SOC/IP/ASIC design team with an emphasis around DFX (DFT/DFD/DFM) Must have expert level, working knowledge about DFX standards and practices, ATPG, Scan, JTAG, iJTAG, BIST, including trade-offs between test quality, test time, efficiency and their impact to overall design implementation Experience with SOC level DFT planning, architecture, and execution. Understanding of industry road map on DFX and active contributions towards improvements in DFX working with industry experts Good focus on automation & infrastructure to enable efficient execution pipeline within DFX function Experience with post silicon debug, yield bring up, test-time and pattern delivery while working closely with TEPE teams for long term strategic improvements Continuous drive to improve flows, methodology and architecture for enabling scalability of the overall team in years to come Understanding of Physical design implementation flows and methods to enable a smooth integration of DFT in the design with efficient and quality hand offs