Sr. Staff Engineer - Timing Methodology

As a Sr. Staff Engineer - Timing Methodology, you will play a critical role in transforming our cutting-edge designs into silicon reality. You will be responsible for all aspects of timing closure from defining methodology, developing flows, closing timing at the block level and timing convergence at SOC level as well.

• In-depth expertise on Timing Methodology and Timing closure both at block level and SOC level in modern Finfet and multi-patterning based process technologies using Cadence Tempus or Synopsys Primetime.


• Own all aspects of timing convergence, including Signoff to build timing correlation, PVTRc corner definition, timing      margining, extraction, signoff timing analysis, glitch noise analysis, timing ECOs and interplay and tradeoff with power. 


• Own, define and drive constraints in collaboration with RTL and IP Vendors.Have in-depth understanding of all timing collaterals for different type of  Ips, namely, hard IP, Stdcell and Memory etc.


• Partner with post-si bringup and testing to ensure pre-si timing correlates well to post-si.


• Collaborate closely with RTL designers, DFT and other stakeholders to achieve best in class PPA. 


• Continuously improve timing analysis methodologies and scripts to enhance efficiency and flow consistency. Stay at the forefront of  advancements in STA  and new process nodes