Staff Design Verification Engineer, DRAM

Verify DRAM and emerging memory architectures through pattern development, regressions, and functional coverage Build and maintain digital and mixed‑signal test benches, vectors, and flows Debug failures, support design teams, track issues, and drive closure Collaborate with global teams to develop new verification tools and methodologies Lead design projects and mentor junior engineers Bachelor's degree in Electrical or Computer Engineering or equivalent Understanding of CMOS circuit design and mixed‑signal verification Experience with HSPICE, VerilogHDL, FINESIM, and scripting languages Knowledge of SystemVerilog, UVM, and SystemVerilog Assertions Strong debugging skills and clear technical communication Bachelor's degree with 5+ years of experience, or Master's degree with 3+ years Experience with memory product development flows Background in semiconductor cross‑functional collaboration Leadership experience in technical project ownership