Staff Layout Designer, NVEG

Organize and prioritize logistics and resource allocations to meet scheduled deadlines and proactively develop methodologies for issue resolution Contribute to group management and technical innovation Assign resources, schedule tasks, provide direction, and deliver quality-controlled results Contribute to projects in a globally distributed design/layout environment Effectively mentor junior team members Contribute to the improvement of layout efficiency through the development of automation and new methodologies; Lead, plan, and deliver major blocks and product revisions. AS or AAS in Electronics, Electrical Engineering, or a related field plus 10 years of direct experience in semiconductor layout design Deep working knowledge of EDA tools (i.e. Cadence Virtuoso, Synopsys, Calibre) Demonstrate a strong ability to debug problems through root-cause analysis, find effective and efficient solutions, and collaborate with the engineering staff Skilled in developing and applying custom layout, floor‑planning, signal-planning and power‑planning methodologies Strong verbal and written communication skills In-depth understanding of design rules and delivering quality layouts Strong physical verification analysis and debugging skills 15+ years direct experience in semiconductor layout design BS degree in a related field Project leadership in quality optimization, die size shrinkage IC layout design experience with NAND, DRAM and/or SRAM Programming skills and AI experience relevant to layout workflow