System DV Engineer

Develop and enhance DV environments using advanced UVM and simulation methodologies Collaborate with AI teams to introduce ML‑driven automation and workflow innovation Identify opportunities to improve verification flows and system‑level integration Build and maintain models, BFMs, and scripts that support scalable verification Champion DV quality standards and sign‑off practices across teams Deep expertise with simulation tools and advanced UVM verification methods Strong proficiency in SystemVerilog plus SystemC or C++, and scripting languages Experience with EDA tools including APR flows and digital/analog/mixed‑signal simulators Clear understanding of DV quality sign‑off requirements Bachelor's degree in Electrical Engineering, Computer Science, or related field 10+ years of industry experience Experience with DRAM or NAND protocols Familiarity with timing‑accurate models and Bus Functional Models (BFMs) Knowledge of AI/ML concepts and their application to verification workflows Master's degree or higher in a related technical field