VP, Memory Architecture

Owns definition and roadmap for LPDDR5/5X/6/7, HBM2E/3/3E, GDDR6/6X, UFS 4.0/5.0/6.0, NAND, emerging NVM, and related controllers/PHYs. Defines strategy for multi-die and chiplet-based memory architectures including 2.5D/3D stacking and HBM integration. Partners with cross-functional teams to set memory performance targets and ensure delivery of KPIs such as bandwidth, latency, power, thermals, reliability, and BOM cost. Leads memory subsystem optimization for AI, GPU, camera, XR, and automotive workloads. Develops supplier and ecosystem strategies for DRAM, NAND, packaging, and controller vendors. Bachelor's degree in Computer/Electrical Engineering, Computer Science, or related field. Fifteen (15) years of Product Management or related work experience. Six (6) years of leadership experience. Four (4) years of working in a large matrixed organization. Two (2) years of working with operating budgets and/or project financials. Two (2) years of negotiating 3rd party business agreements. Master's degree or PhD in Computer/Electrical Engineering, Computer Science, or related field. Twenty (20) years of Product Management or related work experience. Ten (10) years of leadership experience. Six (6) years of working in a large matrixed organization. Four (4) years of working with operating budgets and/or project financials. Four (4) years of negotiating 3rd party business agreements.