At Nokia of America, we're seeking a talented and motivated ASIC PD Coop to join our NI ON Comp R&D ASICs & Architecture 4B department. In this role, you'll be an integral part of our Physical Design sub-group, supporting various tasks that contribute to the successful tape-out of Nokia's ASICs. Your work will focus on applying data mining and analytics techniques to extract valuable insights from PPA metrics and physical design workflows, helping us optimize our designs and stay at the forefront of technology.
Number of Positions: 1
Duration: 4-8 months
Dates: Jan - May - August 2027
Location: Hybrid in San Jose, CA
EDUCATIONAL RECOMMENDATIONS:
Currently a candidate pursuing a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field with an accredited university in the USA.
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