Design Readiness Engineer

Drive alignment between DRAM design and validation, focusing on root cause analysis to prevent recurrence of known circuit bugs. Collaborate with Design, Verification, and Validation teams to implement corrective actions. Ensure DRAM silicon performance meets manufacturing and design requirements. Validate system-level I/O margin for current and future DRAM products. Develop new testing strategies to improve efficiency and effectiveness of DRAM specification validation. Currently pursuing a degree in Electrical Engineering, Computer Engineering, or a related field. Strong understanding of digital circuit design and validation principles. Analytical approach with attention to detail and problem-solving skills. Ability to work collaboratively across engineering fields. Excellent communication and documentation skills. Experience with DRAM architecture or semiconductor validation workflows. Familiarity with characterization techniques and HMV trim solutions. Exposure to silicon debug tools and methodologies. Interest in innovation and continuous improvement in testing strategies. Prior internship or project experience in memory design or validation.