Digital Design - Summer Internship 2026

Description

• IP level verification and documentation
• Porting current designs and models written in Verilog-2001 to SystemVerilog
• Migration from in-house verification environment to UVM based verification environment
• Proactively assist with any other duties as assigned 

• Currently pursuing a MS in Electrical Engineering, Computer Science or related field.
• Experience with logic design and system FPGA skills; C/C++ and system language skill preferred
• Candidate needs to be familiar with system/IP level verification procedure
• Knowledge and or experience of basic IC hardware and system level mix signal background
• Extensive knowledge of CMOS Image Sensor, ISP algorithm, and CPU/DSP processing is a plus
• Good communication skills and organized documentation capability