Intern - Advanced DRAM Cell/Device Engineer

Develop an understanding of process and device requirements for new memory cell, access device, and selectors and help refine requirements, as necessary. Characterize array and model cell device properties to identify improvement opportunities (product bias setting, process integration, design waveform, etc). Contribute to the cell material and process flow definition, particularly in the area of device physics and array analysis, as well as conntributing to the definition and validation of the cell electrical specifications for product qualification. Understand and develop models for fundamental yield-limiting mechanisms in new memory technologies through statistical data analysis of experiments conducted in semiconductor fab. Evaluate in-line, probe, parametric, and back end data. Correlate array reliability and characterization testing to product reliability. Define, support and gather data on media management techniques, on-chip and in system to improve performance and reliability of end product. Current enrollment in a PhD program with a focus in Device Physics. Must be a current student, must not graduate before September 2026. Ability to collaborate effectively with cross-functional teams, including product, modeling design & process integration engineers, to address cell deficiencies and execute improvement roadmaps. Experience with electrical characterization and failure analysis. Familiarity with DRAM architecture and scaling challenges. Exposure to semiconductor fabrication and process integration. Proficiency in statistical data analysis tools and modeling techniques.