Intern - ASIC Design Verification

Work with UVM-based SystemVerilog testbenches to verify ASIC functionality. Collaborate with verification engineers to drive block, subsystem, or SoC-level verification plans to closure. Apply verification methodologies, flows, and quality metrics to ensure design integrity. Debug complex issues and contribute to problem resolution. Document verification strategies and results for internal stakeholders. Actively pursuing a Bachelor's or Master's degree in Electrical Engineering or Computer Engineering with equivalent experience. Coursework in Digital Logic, Computer Architecture, ASIC Verification, and VLSI. Proficient or working knowledge of object-oriented programming languages such as Python or SystemVerilog. Strong analytical and problem-solving skills. Excellent verbal and written communication abilities. Experience with Python and/or SystemVerilog programming. Familiarity with verification tools and debugging techniques. Ability to work independently and collaboratively in a team environment. Interest in developing high-quality verification components for complex SoC designs. Previous internship or project experience in ASIC design or verification.