Machine Learning for Physical Design Intern - CPU/AI Hardware

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

As an intern in the Physical Design (PD) team, you will work on high-performance designs going into industry leading AI/ML architectures. The student coming into this role will develop ML-based tools and flows to improve the PPA (Performance Power Area) and turnaround time for all aspects of chip implementation from synthesis to tapeout for various IPs. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.

This role is on-site, hybrid, based out of Santa Clara, CA working 4 days in office, 1 day remote. 

Who You Are

What We Need

• Ability to develop ML-based tools to improve PPA and turnaround time for chip implementation.


• Work closely with other PD engineers to develop ML tools for areas such as synthesis, PnR, timing closure, and power grid analysis.


• Responsibility for selecting appropriate datasets, data representation methods, and implementing new algorithms.


• Capability to run machine learning tests, perform statistical analysis, and fine-tune models using test results.

What You Will Learn

• How to apply ML systems and flows to high-performance designs for industry-leading AI/ML architectures.


• Practical experience in extending existing ML systems and implementing cutting-edge algorithms.


• Gain exposure to core physical design fundamentals, including synthesis, place and route, and timing analysis.


• Experience collaborating with a group of highly experienced engineers across various domains of the ASIC implementation.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.